Integrated circuits are an integral part of any electronic device. A variety of integrated circuits are often used together to enable the operation of the electronic device. While integrated circuits are typically designed for a particular application, one type of integrated circuit which enables flexibility is a programmable logic device (PLD). A programmable logic device is designed to be user-programmable so that users may implement logic designs of their choices. One type of programmable logic device is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” having a two-level AND/OR structure connected together and to input/output (I/O) resources by an interconnect switch matrix. Another type of programmable logic device is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose. The configuration data bits may be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
PLDs also have different “modes” depending on the operations being performed on them. A specific protocol allows a programmable logic device to enter into the appropriate mode. Typical PLDs have internal blocks of configuration memory which specify how each of the programmable cells will emulate the user's logic. During a “program” mode, a configuration bitstream is provided to non-volatile memory, such as a read-only memory (ROM) (e.g. a programmable ROM (PROM), an erasable PROM (EPROM), or an electrically erasable PROM (EEPROM)) either external or internal to the programmable logic device. Each address is typically accessed by specifying its row and column addresses. During system power up of a “startup” mode, the configuration bits are successively loaded from the non-volatile memory into static random access memory (SRAM) configuration latches of a configuration logic block.
While PLDs provide many advantages, configuration bitstreams for programming logic may not be compatible between different devices having programmable logic. That is, a configuration bitstream may not be interchangeably used between different programmable logic devices, or even different models of a given programmable logic device. For example, a given configuration bitstream for a Virtex-II device may not be used in a Virtex 4 device, both available from Xilinx, Inc. of San Jose, Calif. Further, a given configuration bitstream may not be used between different models of a Virtex-II device, for example, or different models of a Virtex 4 device. In addition to delays as result of the need to generate separate bitstreams for different devices, there is an additional cost involved generating the additional bitstreams. Further, the need to generate different bitstreams may prevent or delay users from migrating to newer devices of a manufacturer, thereby impacting the performance of the manufacturers.
Accordingly, there is a need for a method of configuring a device having programmable logic which enables a representation of the design to be used in different devices.